diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-12-18 14:22:49 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-15 15:24:31 +0100 |
| commit | c12ef9723efac1006307c7fae13e34cb444cee36 (patch) | |
| tree | 3e8db65dda443509db490c9919bac3a77501871e /src/northbridge/intel/haswell/haswell.h | |
| parent | 6f561afa4a635958dedf20ffda9a40c6f5e5699e (diff) | |
haswell: resource allocation
The previous code w.r.t. resource allocation was getting lucky
based on the way fixed mmio resources on the system were being
chosen. Namely, PCIEXBAR was the lowest mmio space and the other
fixed non-standar BARs were above it. The resource allocator would
then start allocating standard BARs below that.
On top of that other resources were being added when
dev_ops->set_resources() was being called on the PCI domain. At that
point the PCI range limit were already picked for where to start
allocating from.
To ensure we no longer get lucky during resource allocation add the
fixed resources in the host bridge and add the memory controller
cacheable memory areas. With those resources added the range limit
for standard PCI BARs is chosen properly.
Depending on haswell board configurations we may need to adjust and
pass in the size of physical address space needed for PCI resources
to the reference code. For the time being the CRBs appear to be OK.
Lastly, remove the SNB workaround for reserving 2MiB at 1GiB and 512MiB.
Output from 6GiB memory configuration:
MC MAP: TOM: 0x140000000
MC MAP: TOUUD: 0x18f600000
MC MAP: MESEG_BASE: 0x13f000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x13f000000
MC MAP: REMAP_LIMIT: 0x18f5fffff
MC MAP: TOLUD: 0xafa00000
MC MAP: BDSM: 0xada00000
MC MAP: BGSM: 0xad800000
MC MAP: TESGMB: 0xad000000
MC MAP: GGC: 0x209
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000000efffff: RAM
4. 0000000000f00000-0000000000ffffff: RESERVED
5. 0000000001000000-00000000acebffff: RAM
6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
7. 00000000ad000000-00000000af9fffff: RESERVED
8. 00000000f0000000-00000000f3ffffff: RESERVED
9. 00000000fed10000-00000000fed17fff: RESERVED
10. 00000000fed18000-00000000fed18fff: RESERVED
11. 00000000fed19000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-000000018f5fffff: RAM
e820 map has 11 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 0000000000f00000 = 1 RAM
4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
5: 0000000001000000 - 00000000acec0000 = 1 RAM
6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
10: 0000000100000000 - 000000018f600000 = 1 RAM
Output from 4GiB memory configuration:
MC MAP: TOM: 0x100000000
MC MAP: TOUUD: 0x14f600000
MC MAP: MESEG_BASE: 0xff000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x100000000
MC MAP: REMAP_LIMIT: 0x14f5fffff
MC MAP: TOLUD: 0xafa00000
MC MAP: BDSM: 0xada00000
MC MAP: BGSM: 0xad800000
MC MAP: TESGMB: 0xad000000
MC MAP: GGC: 0x209
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000000efffff: RAM
4. 0000000000f00000-0000000000ffffff: RESERVED
5. 0000000001000000-00000000acebffff: RAM
6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
7. 00000000ad000000-00000000af9fffff: RESERVED
8. 00000000f0000000-00000000f3ffffff: RESERVED
9. 00000000fed10000-00000000fed17fff: RESERVED
10. 00000000fed18000-00000000fed18fff: RESERVED
11. 00000000fed19000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-000000014f5fffff: RAM
e820 map has 11 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 0000000000f00000 = 1 RAM
4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
5: 0000000001000000 - 00000000acec0000 = 1 RAM
6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
10: 0000000100000000 - 000000014f600000 = 1 RAM
Output from 2GiB memory configuration:
MC MAP: TOM: 0x40000000
MC MAP: TOUUD: 0x100600000
MC MAP: MESEG_BASE: 0x3f000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x100000000
MC MAP: REMAP_LIMIT: 0x1005fffff
MC MAP: TOLUD: 0x3ea00000
MC MAP: BDSM: 0x3ca00000
MC MAP: BGSM: 0x3c800000
MC MAP: TESGMB: 0x3c000000
MC MAP: GGC: 0x209
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000000efffff: RAM
4. 0000000000f00000-0000000000ffffff: RESERVED
5. 0000000001000000-000000003bebffff: RAM
6. 000000003bec0000-000000003bffffff: CONFIGURATION TABLES
7. 000000003c000000-000000003e9fffff: RESERVED
8. 00000000f0000000-00000000f3ffffff: RESERVED
9. 00000000fed10000-00000000fed17fff: RESERVED
10. 00000000fed18000-00000000fed18fff: RESERVED
11. 00000000fed19000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-00000001005fffff: RAM
e820 map has 11 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 0000000000f00000 = 1 RAM
4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
5: 0000000001000000 - 000000003bec0000 = 1 RAM
6: 000000003bec0000 - 000000003ea00000 = 2 RESERVED
7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
10: 0000000100000000 - 0000000100600000 = 1 RAM
Verified through debug messages that range limits as well as
resources were being properly honored.
Change-Id: I2faa7d8a2a34a6a411a2885afb3b5c3fa1ad9c23
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2687
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/haswell/haswell.h')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 967a186e81..bbb51aaf81 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -63,7 +63,6 @@ #define MCHBAR 0x48 #define PCIEXBAR 0x60 #define DMIBAR 0x68 -#define X60BAR 0x60 #define GGC 0x50 /* GMCH Graphics Control */ @@ -91,8 +90,14 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define TOM 0xa0 +#define MESEG_BASE 0x70 /* Management Engine Base. */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ +#define REMAPBASE 0x90 /* Remap base. */ +#define REMAPLIMIT 0x98 /* Remap limit. */ +#define TOM 0xa0 /* Top of DRAM in memory controller space. */ #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */ |