diff options
| author | Ronald G. Minnich <rminnich@google.com> | 2013-06-25 15:56:46 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-12-05 20:23:23 +0100 |
| commit | 5bcca7e98215d95190274f14d34284f16a6fe194 (patch) | |
| tree | 7e4878a74c756a1e92f68fd69081280bd1502664 /src/northbridge/intel/haswell/haswell.h | |
| parent | 7982de165e87c59df98f8334afc1728e7cc90e7f (diff) | |
haswell: pull in the init code for FUI
Removed two unnecessary register sets, and did the power well a bit
more correctly. Also, added a register definition include file so we can
used constants instead of magic numbers.
We also set registers to common initialized values that are
needed for FUI, VBIOS, and kernel. This set of registers
appears to be an absolute bare minimum. Since we're hoping to use
FUI for all chipsets from this one forward, we unconditionally do the
setting here.
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Change-Id: Ife3f661ba010214d92b646b336f2b06645119f17
Reviewed-on: https://gerrit.chromium.org/gerrit/59988
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4328
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/haswell.h')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 96438adec8..b3502267a5 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -123,7 +123,6 @@ #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) #define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) -#define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define BIOS_RESET_CPL 0x5da8 /* 8bit */ /* |