aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/haswell/haswell.h
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-07-03 12:29:03 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-11 20:49:25 +0000
commit73fa035b2053870776c9c81a821b6a1603dc13f1 (patch)
tree8cd4215b0bdcfd13146de90c43af2533a363acb7 /src/northbridge/intel/haswell/haswell.h
parentc06648b8c1f33e0f9d2356edc740e7661b7eb4f2 (diff)
nb/intel/haswell: Add `mb_late_romstage_setup` function
This function is called at the end of `romstage_common`. Only one board makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call it after `romstage_common` has done nearly everything. Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/haswell.h')
-rw-r--r--src/northbridge/intel/haswell/haswell.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index fa32ecad7c..7fb24c8935 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -195,6 +195,7 @@ struct romstage_params {
void (*copy_spd)(struct pei_data *peid);
};
void romstage_common(const struct romstage_params *params);
+void mb_late_romstage_setup(void); /* optional */
void haswell_early_initialization(void);
void haswell_late_initialization(void);