diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 14:46:47 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 09:58:33 +0000 |
| commit | 45f448f4a4e09b270d964c98d3aced2e73d9d6bc (patch) | |
| tree | d217f38c8a28fbf1c449f17f243b73a7f23db6dd /src/northbridge/intel/haswell/haswell.h | |
| parent | c05c2b3fb25ca42a75ecc987178c298f7fe0ead5 (diff) | |
haswell: Relocate `mainboard_romstage_entry` to northbridge
This is what sandybridge does, and if done properly allows factoring out
common settings. Said refactoring will be handled in subsequent commits.
Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/northbridge/intel/haswell/haswell.h')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 6eb8de5ea1..baa4f32614 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -189,8 +189,6 @@ void intel_northbridge_haswell_finalize_smm(void); -struct pei_data; -void romstage_common(struct pei_data *pei_data); void mb_late_romstage_setup(void); /* optional */ void haswell_early_initialization(void); |