aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/haswell/haswell.h
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-07-03 12:06:04 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-08 22:16:58 +0000
commit2e25ac6afe84d9535fa6d89b847915e96f5d266b (patch)
tree3c05edec71d4e1215d864eccb61a9ae0a0b7717e /src/northbridge/intel/haswell/haswell.h
parent284a54775bf17f5192b164a4b9d09a06fcd747cd (diff)
haswell: relocate `romstage_common` to northbridge
Other platforms do this as well. It will ease refactoring on follow-ups. Change-Id: I643982a58c6f5370c78acef93740f27df001a06d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/northbridge/intel/haswell/haswell.h')
-rw-r--r--src/northbridge/intel/haswell/haswell.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index c3930493da..b98d88085e 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -189,6 +189,16 @@
void intel_northbridge_haswell_finalize_smm(void);
+struct pei_data;
+struct rcba_config_instruction;
+struct romstage_params {
+ struct pei_data *pei_data;
+ const void *gpio_map;
+ const struct rcba_config_instruction *rcba_config;
+ void (*copy_spd)(struct pei_data *peid);
+};
+void romstage_common(const struct romstage_params *params);
+
void haswell_early_initialization(void);
void haswell_late_initialization(void);
void set_translation_table(int start, int end, u64 base, int inc);