fox_wtm2: First step support for coreboot-based graphics startup

This code is the initial version of FUI for haswell and wtm2.

The code is simplified from before in many ways. I've gotten rid of
the opcode table, because it obscured meaning and I don't think it is
needed any more. Register sets, mainly used for reset, are just lines
of code -- not many of them. There are a bunch of not-yet-documented
registers here; the VBIOS seemed to think they were necessary and
testing shows they seem to be right.

As a bit of added paranoia, we always include the VBIOS code as our
emergency recovery path. You have to run it now anyways, so this is no
regression from our current situation; and, if all goes well, in a
week (or so), you'll never have to run it again, but like the Force
and nose hair, it will be with you always.

The code can return in three ways. The first, best way is success:
panel is up and the VBIOS need not run. The second mode is that we
tried to light up the panel but could not, for some reason, but will
return with the panel partly up. In this case, it's ok not to power
cycle the panel. The third, worst case, which will NEVER happen, ha
ha, is that we have to turn the panel off and wait the required 600ms
for it to cycle. Life sucks sometimes. This failure mode is in the
'hang on we're going to fix it' category now that we have ramstage in
RW.

The Big Goal here is to create something other coreboot ports can use
as well. The guys doing the x60 report that the link FUI works,
without too many mods, on that chipset, so it seems Intel is keeping
things from changing too much over time.

Also, again, please note: this and the next 3 versions will ALWAYS fail.
The goal is to verify the correctness of the recovery path.

The bizarre tab-space formatting in drm_dp_helper.h is from the original,
as in i915_reg.h

Change-Id: I6ecf454633029d185c29d470980b5a0f3114a8ce
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 10 insertions, 10 deletions

diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index dd06867d9c..e577fb52f7 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Chromium OS Authors
+ * Copyright 2012 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -189,6 +189,7 @@ static void gma_pm_init_post_vbios(struct device *dev)
 
 static void gma_func0_init(struct device *dev)
 {
+	int lightup_ok = 0;
 	u32 reg32;
 	u32 graphics_base; //, graphics_size;
 	/* IGD needs to be Bus Master */
@@ -205,14 +206,6 @@ static void gma_func0_init(struct device *dev)
 	/* Init graphics power management */
 	gma_pm_init_pre_vbios(dev);
 
-	/* PCI Init, will run VBIOS */
-#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
-	printk(BIOS_SPEW, "Run the VBIOS init\n");
-	pci_dev_init(dev);
-#endif
-
-	/* Post VBIOS init */
-	gma_pm_init_post_vbios(dev);
 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
 	printk(BIOS_SPEW, "NATIVE graphics, run native enable\n");
 	u32 iobase, mmiobase, physbase;
@@ -221,8 +214,15 @@ static void gma_func0_init(struct device *dev)
 	physbase = pci_read_config32(dev, 0x5c) & ~0xf;
 
 	int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
-	i915lightup(physbase, iobase, mmiobase, graphics_base);
+	lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base);
 #endif
+	if (! lightup_ok) {
+		printk(BIOS_SPEW, "FUI did not run; using VBIOS\n");
+		pci_dev_init(dev);
+	}
+
+	/* Post VBIOS init */
+	gma_pm_init_post_vbios(dev);
 }
 
 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)