diff options
| author | Tristan Corrick <tristan@corrick.kiwi> | 2018-10-31 02:27:29 +1300 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-01 22:23:52 +0000 |
| commit | 1a73eb08e79b4a53702ff9e9103bb3352391892b (patch) | |
| tree | db1a824ac9abb5ee78f96bda5dabc7dd2d3dc2f1 /src/northbridge/intel/haswell/gma.c | |
| parent | fdf907e4405e5df84e9d5a29735e0506782d9c6d (diff) | |
nb/intel/haswell/gma: Support boards that have DDI E connected
On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to
initialise the display when lanes are not configured to be shared
between DDI A and DDI E.
Intel's reference manual [1] states that the decision to share lanes
between DDI A and DDI E is "based on board configuration". Hence, add a
new field to the devicetree that boards can set. All existing Haswell
boards have this unset, thus taking a value of 0, so there is no change
to existing behaviour.
[1]: Intel Open Source Graphics Programmer's Reference Manual (PRM)
Volume 2c: Command Reference: Registers (Haswell)
https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013-intel-core-processor-family
Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29385
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/gma.c')
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index efc9fa3bd5..f4cec68c06 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -368,7 +368,10 @@ static void gma_setup_panel(struct device *dev) bit 4: DDI A supports 4 lanes and DDI E is not used bit 7: DDI buffer is idle */ - gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED); + reg32 = DDI_BUF_IS_IDLE | DDI_INIT_DISPLAY_DETECTED; + if (!conf->gpu_ddi_e_connected) + reg32 |= DDI_A_4_LANES; + gtt_write(DDI_BUF_CTL_A, reg32); /* Set FDI registers - is this required? */ gtt_write(_FDI_RXA_MISC, 0x00200090); |