diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2017-06-30 14:52:01 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2017-07-12 16:10:43 +0000 |
| commit | 19c2ad87588aff19a1213eedc3c34f14a99b1ad4 (patch) | |
| tree | aa59afac685ede30502602a61b1a70ae1136ebe6 /src/northbridge/intel/haswell/gma.c | |
| parent | bdae93571b4d54a149023ac1e208cfdee7561411 (diff) | |
drv/intel/gma/opregion: Add interface for GNVS ASLB handling
Add and use new interface to set and get GNVS' ASLB register.
To be used by Intel's gma driver to set ASLB at ACPI table
creation and to get ASLB on S3 resume.
Change-Id: If30c6b2270069783b0892774802f47406404da5f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/haswell/gma.c')
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 75f3b7a944..6cd1f6f1d7 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -215,6 +215,19 @@ int gtt_poll(u32 reg, u32 mask, u32 value) return 0; } +uintptr_t gma_get_gnvs_aslb(const void *gnvs) +{ + const global_nvs_t *gnvs_ptr = gnvs; + return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); +} + +void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) +{ + global_nvs_t *gnvs_ptr = gnvs; + if (gnvs_ptr) + gnvs_ptr->aslb = aslb; +} + static void power_well_enable(void) { gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); @@ -527,7 +540,7 @@ gma_write_acpi_tables(struct device *const dev, gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gnvs->aslb = (u32)(uintptr_t)opregion; + gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } |