diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-15 00:49:03 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 12:54:00 +0000 |
| commit | 1db5bc7dac2bb592708f26dede339ffdf3246567 (patch) | |
| tree | d8636a114ebd6ef6830a016de15c92b21f0b740d /src/northbridge/intel/haswell/chip.h | |
| parent | 3663d55a23fb64ea88dd1fd18ae4b0ce29e71a61 (diff) | |
nb/intel/haswell: Tidy up code and comments
- Reformat some lines of code
- Put names to all used MCHBAR registers
- Move MCHBAR registers into a separate file, for future expansion
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
Tested, it does not change the binary of Asrock B85M Pro4.
Change-Id: I926289304acb834f9b13cd7902801798f8ee478a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/chip.h')
| -rw-r--r-- | src/northbridge/intel/haswell/chip.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 506aaa58e8..27227916f6 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -20,9 +20,9 @@ /* * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse + * 0x04 = Enabled, 2ms short pulse * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse + * 0x06 = Enabled, 6ms short pulse * 0x07 = Enabled, 100ms short pulse */ struct northbridge_intel_haswell_config { |