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authorArthur Heymans <arthur@aheymans.xyz>2018-01-27 13:39:12 +0100
committerMartin Roth <martinroth@google.com>2018-02-06 16:13:49 +0000
commitf300f362103306775dab4fd994ca5e9fd59b96e4 (patch)
tree166091b503338368b4b50dde5165903fbda64ac5 /src/northbridge/intel/haswell/Kconfig
parent485c0ad0783aa168feab8944e498a393774512fd (diff)
nb/intel/haswell: Use the common MRC cache driver
This driver uses an fmap region for the MRC cache instead of a CBFS file which makes it easier to manage if one wants to write protect it. Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/haswell/Kconfig')
-rw-r--r--src/northbridge/intel/haswell/Kconfig7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index d5dec53041..5c8caea92d 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -16,7 +16,7 @@
config NORTHBRIDGE_INTEL_HASWELL
bool
select CPU_INTEL_HASWELL
- select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
+ select CACHE_MRC_SETTINGS
select INTEL_DDI
select INTEL_GMA_ACPI
select RELOCATABLE_RAMSTAGE
@@ -39,11 +39,6 @@ config CACHE_MRC_SIZE_KB
int
default 512
-config MRC_CACHE_SIZE
- hex
- depends on !CHROMEOS
- default 0x10000
-
config DCACHE_RAM_BASE
hex
default 0xff7c0000