diff options
| author | Joel Kitching <kitching@google.com> | 2019-04-30 13:13:40 +0800 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-05-03 14:32:06 +0000 |
| commit | 82d73e2d5a44bee097d02d41a450f5bfd703bd5b (patch) | |
| tree | 23804f47c8b9276f2382e2ffd82e0d020744acbc /src/northbridge/intel/haswell/Kconfig | |
| parent | c0fe0b28a9461e963d6dff5d91cf70231dcae0e8 (diff) | |
nb/intel/haswell: correct a typo in Kconfig
Change-Id: I115e065ce11946b85571e7233203be68c1789d70
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/Kconfig')
| -rw-r--r-- | src/northbridge/intel/haswell/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 8c1e0b18f7..e1067c5949 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -37,7 +37,7 @@ config HASWELL_VBOOT_IN_BOOTBLOCK Haswell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. - Haswell however uses a mrc.bin to initialse memory which + Haswell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region |