diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-08-06 15:50:54 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-24 10:04:41 +0000 |
| commit | d522db048b1e1b6e61f585859d7a95b308cb53de (patch) | |
| tree | aad6c38b60e7b8093a0c9b49a8694dfc02e25efe /src/northbridge/intel/gm45 | |
| parent | cf2941aec237535ff76961646ad67b71f0a03a60 (diff) | |
nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware
8M was set in the assumption that at least 4M was needed for IED
(Intel Enhanced Debug) , but this is not true.
The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG
is only 2M. Also at most 6M of RAM more becomes available for use.
Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27873
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 03f617c6a3..d067dc2ff9 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1242,12 +1242,13 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode uma_sizem = (gms_sizek + gsm_sizek) >> 10; } - /* TSEG 8M */ + /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, + which requires to have TSEG_BASE aligned to TSEG_SIZE. */ u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); reg8 &= ~0x7; - reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); - uma_sizem += 8; + uma_sizem += 2; } const unsigned int mmio_size = get_mmio_size(); |