Rename ECAM-specific MMCONF Kconfigs

Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space.  Some platforms have a different way of mapping the PCI config
space to memory.  This patch renames the following configs to
make it clear that these configs are ECAM-specific:

- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH

Please refer to CB:57861 "Proposed coreboot Changes" for more
details.

BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
     Make sure Jenkins verifies that builds on other boards

Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

3 files changed, 7 insertions, 7 deletions

diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index e3675db2f0..3f632a1a6f 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -23,10 +23,10 @@ config VGA_BIOS_ID
 	string
 	default "8086,2a42"
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xf0000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	int
 	default 64
 
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index 43d73e922d..c4636beb3e 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -16,7 +16,7 @@ Device (PDRC)
 		Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
 		Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
 		Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE,  0x00001000)
-		Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+		Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
 		Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
 		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
 		Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index a9a1e8eb2d..eb1aa0a277 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -9,7 +9,7 @@
 
 static uint32_t encode_pciexbar_length(void)
 {
-	switch (CONFIG_MMCONF_BUS_NUMBER) {
+	switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
 		case 256: return 0 << 1;
 		case 128: return 1 << 1;
 		case  64: return 2 << 1;
@@ -21,17 +21,17 @@ void bootblock_early_northbridge_init(void)
 {
 	/*
 	 * The "io" variant of the config access is explicitly used to
-	 * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
+	 * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to
 	 * true. That way all subsequent non-explicit config accesses use
 	 * MCFG. This code also assumes that bootblock_northbridge_init() is
 	 * the first thing called in the non-asm boot block code. The final
 	 * assumption is that no assembly code is using the
-	 * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+	 * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
 	 *
 	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
 	 * 4GiB.
 	 */
-	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
 	pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0);
 	pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
 }