diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-28 13:56:18 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-05 09:39:08 +0000 |
| commit | 6e732d34a0c1b87803925065b66076599c1e5642 (patch) | |
| tree | 2e3d33bc34b934edab5ebd0a5af9146b9ec8f482 /src/northbridge/intel/gm45 | |
| parent | 6e0ca68c82fe2285e7f6c8fc22711d4a4c65aa2a (diff) | |
intel: Turn `DEFAULT_RCBA` into a Kconfig symbol
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290
Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/acpi/gm45.asl | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 7f642194ba..8c5fb499ee 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -3,7 +3,6 @@ #include "hostbridge.asl" #include "../memmap.h" #include <southbridge/intel/i82801ix/i82801ix.h> -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -14,7 +13,7 @@ Device (PDRC) // This does not seem to work correctly yet - set values statically for // now. Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index fd7ce527a1..f2c0090ed5 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -264,7 +264,7 @@ static void setup_rcrb(const int peg_enabled) /* Link1: target port 0, component id 2 (ICH), link valid. */ DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0); - DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = |