diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2023-09-17 09:49:43 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-08 13:03:45 +0000 |
| commit | 0509009f7986152dc2407fe98dbdfe9aa6eb355a (patch) | |
| tree | d258eaf7a5b2d6d4debbc912b09d838da59a9e13 /src/northbridge/intel/gm45 | |
| parent | 0d50536a50d217813d0e9f6dc04ed106d289e062 (diff) | |
nb/intel/gm45/raminit: Use read32p()
Built roda/rk9 with BUILD_TIMELESS=1 and the resulting coreboot.rom
remains identical.
Change-Id: Ib1e7144eebf8148c4eb5cc0e7bc03ae3d7281092
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77971
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index a998d771c8..b7e013959a 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1965,7 +1965,7 @@ static void jedec_init_ddr2(const timings_t *const timings, jedec_command(rankaddr, DCC_CMD_ABP, 0); jedec_command(rankaddr, DCC_CMD_CBR, 0); udelay(1); - read32((void *)(rankaddr)); + read32p(rankaddr); jedec_command(rankaddr, DCC_SET_MREG, WR | CAS | BTinterleaved | BL8); jedec_command(rankaddr, DCC_SET_EREGx(1), OCDdefault | ODT_150OHMS); |