diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:41:06 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 16:32:10 +0000 |
| commit | dddd1cc6913bd0cbb814b68de7315cb84bfb9c2f (patch) | |
| tree | e4ad63b1db7fbeaf14ad5bf60046a0ed063b86a5 /src/northbridge/intel/gm45 | |
| parent | 7aa3372ce21565962d4cb1090e1f194b6f33f968 (diff) | |
src/northbridge: Drop unneeded empty lines
Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/gm45.h | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 5 |
3 files changed, 0 insertions, 13 deletions
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index d18b3d42c8..dc993cfb3c 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -170,7 +170,6 @@ enum { #define CMOS_WRITE_TRAINING 0x90 /* 16 bytes (could be reduced to 10 bytes) */ - #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed14000) #define DEFAULT_DMIBAR ((u8 *)0xfed18000) @@ -181,7 +180,6 @@ enum { #define DEFAULT_EPBAR 0xfed19000 #define DEFAULT_HECIBAR ((u8 *)0xfed1a000) - #define IOMMU_BASE1 0xfed90000 #define IOMMU_BASE2 0xfed91000 #define IOMMU_BASE3 0xfed92000 @@ -358,7 +356,6 @@ enum { #define CxDTAEW(x) (0x1280+(x*0x100)) #define CxDTC(x) (0x1288+(x*0x100)) - /* * DMIBAR */ @@ -376,7 +373,6 @@ enum { #define DMILE2D 0x60 #define DMILE2A 0x68 - /* * EPBAR */ @@ -390,7 +386,6 @@ enum { #define EPLE1A 0x58 #define EPLE2D 0x60 - #ifndef __ACPI__ void gm45_early_init(void); void gm45_early_reset(void); diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 88c3cee117..5a4999e4b0 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -217,7 +217,6 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) pci_update_config32(pciex, 0xb04, ~(0x03 << 29), 0x01 << 29); } - /*\ Setup ASPM on DMI \*/ /* Exit latencies should be checked to be supported by @@ -232,7 +231,6 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) DMIBAR8(0x208 + 3) = 0; DMIBAR32(0x208) &= ~(3 << 20); - /*\ Setup ASPM on PEG \*/ /* * Maybe we just have to advertise ASPM through LCAP[11:10] @@ -258,7 +256,6 @@ static void setup_rcrb(const int peg_enabled) /* Link2: link_valid. */ EPBAR8(EPLE2D) |= (1 << 0); /* link valid */ - /*\ RCRB setup: DMI Port \*/ /* Set component ID of MCH (1). */ diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index b95e5631b9..7fc97f01a1 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -216,7 +216,6 @@ void enter_raminit_or_reset(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 | (1 << 7)); } - /* For a detected DIMM, test the value of an SPD byte to match the expected value after masking some bits. */ static int test_dimm(sysinfo_t *const sysinfo, @@ -281,7 +280,6 @@ static void verify_ddr3(sysinfo_t *const sysinfo, int mask) } } - typedef struct { int dimm_mask; struct { @@ -1710,7 +1708,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Check for bad warm boot. */ reset_on_bad_warmboot(); - /***** From now on, program according to collected infos: *****/ /* Program DRAM type. */ @@ -1772,10 +1769,8 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); - /* Take a breath (the reader). */ - /* Perform ZQ calibration for DDR3. */ if (sysinfo->spd_type == DDR3) ddr3_calibrate_zq(); |