aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/gm45
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-08 09:56:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-09 12:48:46 +0000
commit8abf66e4e06412db08918dcde31f2d515040a409 (patch)
tree42f13869f4a0da507452ea66f1bca9dad89f05cc /src/northbridge/intel/gm45
parent4d372c7353727e9ffce9ec4e6b2de3cd6ab8e320 (diff)
cpu/x86: Flip SMM_TSEG default
This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index f1318ebc93..c3d24820a5 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select INTEL_GMA_SSC_ALTERNATE_REF
select POSTCAR_STAGE
select POSTCAR_CONSOLE
- select SMM_TSEG
select PARALLEL_MP
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM