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authorPatrick Georgi <pgeorgi@google.com>2020-05-10 16:41:01 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-11 17:11:40 +0000
commit6b5bc77c9b22c398262ff3f4dae3e14904c57366 (patch)
treeab40c703d92f906f8604635f091f809b59233efa /src/northbridge/intel/gm45
parenta83c6bc907b8ef77935ba62789bc4ed60716986d (diff)
treewide: Remove "this file is part of" lines
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/Kconfig1
-rw-r--r--src/northbridge/intel/gm45/Makefile.inc1
-rw-r--r--src/northbridge/intel/gm45/acpi.c1
-rw-r--r--src/northbridge/intel/gm45/acpi/gm45.asl1
-rw-r--r--src/northbridge/intel/gm45/acpi/hostbridge.asl1
-rw-r--r--src/northbridge/intel/gm45/acpi/peg.asl1
-rw-r--r--src/northbridge/intel/gm45/bootblock.c1
-rw-r--r--src/northbridge/intel/gm45/chip.h1
-rw-r--r--src/northbridge/intel/gm45/early_init.c1
-rw-r--r--src/northbridge/intel/gm45/early_reset.c1
-rw-r--r--src/northbridge/intel/gm45/gm45.h1
-rw-r--r--src/northbridge/intel/gm45/gma.c1
-rw-r--r--src/northbridge/intel/gm45/igd.c1
-rw-r--r--src/northbridge/intel/gm45/iommu.c1
-rw-r--r--src/northbridge/intel/gm45/memmap.c1
-rw-r--r--src/northbridge/intel/gm45/northbridge.c1
-rw-r--r--src/northbridge/intel/gm45/pcie.c1
-rw-r--r--src/northbridge/intel/gm45/pm.c1
-rw-r--r--src/northbridge/intel/gm45/raminit.c1
-rw-r--r--src/northbridge/intel/gm45/raminit_rcomp_calibration.c1
-rw-r--r--src/northbridge/intel/gm45/raminit_read_write_training.c1
-rw-r--r--src/northbridge/intel/gm45/raminit_receive_enable_calibration.c1
-rw-r--r--src/northbridge/intel/gm45/romstage.c1
-rw-r--r--src/northbridge/intel/gm45/thermal.c1
24 files changed, 0 insertions, 24 deletions
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 7edea51dfd..f5d6712386 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -1,4 +1,3 @@
-# This file is part of the coreboot project.
# SPDX-License-Identifier: GPL-2.0-only
config NORTHBRIDGE_INTEL_GM45
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index 9228a1f4e2..17e510822a 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -1,5 +1,4 @@
#
-# This file is part of the coreboot project.
#
#
# SPDX-License-Identifier: GPL-2.0-only
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c
index c81d21f0d0..7a5d0b1ce5 100644
--- a/src/northbridge/intel/gm45/acpi.c
+++ b/src/northbridge/intel/gm45/acpi.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <types.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index 270ad90c32..7d64200ddb 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include "hostbridge.asl"
#include "../gm45.h"
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl
index d09d44dfb0..bafedff2c8 100644
--- a/src/northbridge/intel/gm45/acpi/hostbridge.asl
+++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <arch/ioapic.h>
diff --git a/src/northbridge/intel/gm45/acpi/peg.asl b/src/northbridge/intel/gm45/acpi/peg.asl
index 7dc67183b2..f85a22c08b 100644
--- a/src/northbridge/intel/gm45/acpi/peg.asl
+++ b/src/northbridge/intel/gm45/acpi/peg.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
Device (PEGP)
{
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index b10a75d454..e74354ebdb 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <arch/bootblock.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h
index a8a549d72e..0d09bb40ef 100644
--- a/src/northbridge/intel/gm45/chip.h
+++ b/src/northbridge/intel/gm45/chip.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H
#define NORTHBRIDGE_INTEL_GM45_CHIP_H
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 712932aad5..1be351890b 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index eff89bfd3d..44917465d6 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <types.h>
#include <cf9_reset.h>
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 423a8f25eb..d9cfbf7090 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__
#define __NORTHBRIDGE_INTEL_GM45_GM45_H__
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 8a38bdf4ea..0c97b64b39 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <device/mmio.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index 173af1bc5c..10a6f84875 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <stddef.h>
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 4d88e3609d..422655409a 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <string.h>
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 0d03731d47..4fe3998bee 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index d566120827..cd64dfe3dd 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <cbmem.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 0337c55e58..2cab42f4bb 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <stddef.h>
diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c
index 5e03a3ca12..6033c0aca2 100644
--- a/src/northbridge/intel/gm45/pm.c
+++ b/src/northbridge/intel/gm45/pm.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <stddef.h>
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index e6582ad53c..fbf9f01cfa 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <commonlib/helpers.h>
#include <stdint.h>
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
index ee6544b9d2..94da2dc589 100644
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <delay.h>
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index 38a48d96d3..e8d719fca6 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <device/mmio.h>
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index c6c092ba2a..6d95b3401b 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <device/mmio.h>
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 9bfb4e99bb..f7998c926a 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <cbmem.h>
#include <romstage_handoff.h>
diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c
index 73164946ad..ed1ec959bd 100644
--- a/src/northbridge/intel/gm45/thermal.c
+++ b/src/northbridge/intel/gm45/thermal.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <stddef.h>