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authorRonald G. Minnich <rminnich@gmail.com>2013-05-08 17:08:55 +0200
committerRonald G. Minnich <rminnich@gmail.com>2013-05-25 14:22:06 +0200
commit5750fddcba16101e39bf9ec739d9a8bc8e2c0ae9 (patch)
treeedf7dcb2d0fd756a784a547d6163f8f8c412bcd8 /src/northbridge/intel/gm45
parent60c54cc017becb842156644bcda2591a13ba10bc (diff)
Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`
multiply_to_tsc was being copied everywhere, which is bad practice. Put it in the tsc.h include file where it belongs. Delete the copies of it. Per secunet, no copyright notice is needed. This might be a good time to get a copyright notice into tsc.h anyway. Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3242 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/delay.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c
index 9f49c6ed1b..a861e250c2 100644
--- a/src/northbridge/intel/gm45/delay.c
+++ b/src/northbridge/intel/gm45/delay.c
@@ -2,7 +2,6 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
- * 2012 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,17 +23,6 @@
#include <cpu/intel/speedstep.h>
#include "delay.h"
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
-static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
-{
- tsc->lo = (a & 0xffff) * (b & 0xffff);
- tsc->hi = ((tsc->lo >> 16)
- + ((a & 0xffff) * (b >> 16))
- + ((b & 0xffff) * (a >> 16)));
- tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
- tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
-}
-
/**
* Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
*/