diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-28 21:05:26 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:28:48 +0200 |
| commit | 15279a9696c70b82c2223264a505da9122f9aa7b (patch) | |
| tree | 7038d85ab02e392f86a618c49f3db31e14d250f0 /src/northbridge/intel/gm45 | |
| parent | 585d1a0e7d0025e459a35b470572bcdbfff4e3c8 (diff) | |
src/northbridge: Capitalize CPU, RAM and ROM
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/early_reset.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index b24e3a6c06..c987cb3e2c 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -64,6 +64,6 @@ void gm45_early_reset(void/*const timings_t *const timings*/) /* Perform system reset through CF9 interface. */ outb(0x02, 0xcf9); /* Set system reset bit. */ - outb(0x06, 0xcf9); /* Set cpu reset bit, too. */ + outb(0x06, 0xcf9); /* Set CPU reset bit, too. */ halt(); } |