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authorPatrick Georgi <patrick@georgi-clan.de>2013-02-09 15:56:04 +0100
committerPatrick Georgi <patrick@georgi-clan.de>2013-02-11 20:51:33 +0100
commit8cc846897132f6d6baa49118005815aefb5f560f (patch)
tree113b69cccb4728084be3c5f83f04fe9f56db43e5 /src/northbridge/intel/gm45
parent3b19cbae37ab340bd530e35412800a171733fda6 (diff)
Intel: Replace MSR 0xcd with MSR_FSB_FREQ
And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/delay.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c
index 50bea2c1c8..c33bbe2bf0 100644
--- a/src/northbridge/intel/gm45/delay.c
+++ b/src/northbridge/intel/gm45/delay.c
@@ -21,6 +21,7 @@
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
#include "delay.h"
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
@@ -45,7 +46,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total)
u32 fsb = 0, divisor;
u32 d; /* ticks per us */
- msr = rdmsr(0xcd);
+ msr = rdmsr(MSR_FSB_FREQ);
switch (msr.lo & 0x07) {
case 5:
fsb = 400;