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authorArthur Heymans <arthur@aheymans.xyz>2019-10-12 14:18:18 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-10-14 08:15:49 +0000
commit9ed0df4c380dc56a81a59a104b1ccac19cd52c35 (patch)
treece96a0374015a55cf9a44e3fc490c1e70c39b236 /src/northbridge/intel/gm45/romstage.c
parentd3a1a4171ee9f64f7721660f185b649ef874cc15 (diff)
sb/intel/i82801ix: Add common code to set up LPC IO decode ranges
This does the following: - Add gen[1-4]_dec options to the devicetree to set up generic LPC decode ranges in the southbridge code. - Move setting up some default decode ranges to a common place. If somehow a board needs to override this behavior it can happen in the mb_setup_superio() hook (that will be renamed when moving to C_ENVIRONMENT_BOOTBLOCK). Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/gm45/romstage.c')
-rw-r--r--src/northbridge/intel/gm45/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index c853a3a1f4..7f45ca7f83 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -62,7 +62,7 @@ void mainboard_romstage_entry(void)
i82801ix_early_init();
setup_pch_gpios(&mainboard_gpio_map);
- mb_setup_lpc();
+ i82801ix_lpc_decode();
mb_setup_superio();