diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-16 12:50:59 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-24 20:42:07 +0000 |
| commit | 3e33be2e69267b2212a98579f16643fe3c51b6b1 (patch) | |
| tree | 189528763ec6c87a4f3b23eb2217d28757e314b9 /src/northbridge/intel/gm45/raminit.c | |
| parent | 6642b44b292c9cbbf83905ed89aa00b19c79ddca (diff) | |
nb/intel/gm45: Add more DMIBAR/EPBAR registers
Add definitions for more DMIBAR/EPBAR registers, and specify their sizes
as well. Also, expand a comment as the registers' purpose is now known.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45448
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/raminit.c')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 7fc97f01a1..f9d7c8fbed 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1128,7 +1128,7 @@ static void clock_crossing_setup(const fsb_clock_t fsb, } } -/* Program egress VC1 timings. */ +/* Program egress VC1 isoch timings. */ static void vc1_program_timings(const fsb_clock_t fsb) { const u32 timings_by_fsb[][2] = { @@ -1136,9 +1136,9 @@ static void vc1_program_timings(const fsb_clock_t fsb) /* FSB 800MHz */ { 0x14, 0x00f000f0 }, /* FSB 667MHz */ { 0x10, 0x00c000c0 }, }; - EPBAR8(0x2c) = timings_by_fsb[fsb][0]; - EPBAR32(0x38) = timings_by_fsb[fsb][1]; - EPBAR32(0x3c) = timings_by_fsb[fsb][1]; + EPBAR8(EPVC1ITC) = timings_by_fsb[fsb][0]; + EPBAR32(EPVC1IST + 0) = timings_by_fsb[fsb][1]; + EPBAR32(EPVC1IST + 4) = timings_by_fsb[fsb][1]; } #define DEFAULT_PCI_MMIO_SIZE 2048 |