diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-02 11:56:39 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-04 19:15:55 +0200 |
| commit | 7db506c3dd70f9ac0e8cdc481a47fa3835538be2 (patch) | |
| tree | 954275c199955bdee8b7b0d08aaba698e230f34e /src/northbridge/intel/gm45/pcie.c | |
| parent | fb190ed764450208c393a43da4ab15b0f9ccbe58 (diff) | |
src/northbridge: Remove unnecessary whitespace
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/gm45/pcie.c')
| -rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 3f56b94945..47203b4186 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -49,12 +49,12 @@ static void init_egress(void) EPBAR32(0x11c) = 0x00005555; EPBAR32(0x20) |= 1 << 16; - while ((EPBAR8(0x26) & 1) != 0) ; + while ((EPBAR8(0x26) & 1) != 0); /* VC1: enable */ EPBAR32(0x20) |= 1 << 31; - while ((EPBAR8(0x26) & 2) != 0) ; + while ((EPBAR8(0x26) & 2) != 0); } /* MCH side */ @@ -72,7 +72,7 @@ static void init_dmi(int b2step) /* VC1: enable */ DMIBAR32(0x20) |= 1 << 31; - while ((DMIBAR8(0x26) & 2) != 0) ; + while ((DMIBAR8(0x26) & 2) != 0); /* additional configuration. */ DMIBAR32(0x200) |= 3 << 13; |