diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 00:36:31 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-07 20:20:00 +0000 |
| commit | f462b3d379198c968467053f570d6a40c9c8a715 (patch) | |
| tree | 06da018e6740df91f9d7fcbd9d18fa600efcc2dd /src/northbridge/intel/gm45/pcie.c | |
| parent | dd1fb4e38c209f4713d80ae192bd8f4cb4ed0e32 (diff) | |
nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors
These accessors can be reused for several other northbridges.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/pcie.c')
| -rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index f2c0090ed5..4ccd2d61ff 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -251,7 +251,7 @@ static void setup_rcrb(const int peg_enabled) /* Link1: component ID 1, link valid. */ EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0); - EPBAR32(EPLE1A) = DEFAULT_DMIBAR; + EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; if (peg_enabled) /* Link2: link_valid. */ @@ -269,7 +269,7 @@ static void setup_rcrb(const int peg_enabled) /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = (DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = DEFAULT_MCHBAR; + DMIBAR32(DMILE2A) = CONFIG_FIXED_MCHBAR_MMIO_BASE; } void gm45_late_init(const stepping_t stepping) |