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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-11-27 14:06:21 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-03 10:16:18 +0000 |
| commit | 009518e79b9b3a7d756243dd6ca1b6789de1430a (patch) | |
| tree | 1d3096e2a4a780367a6de1798319fada8e0987b7 /src/northbridge/intel/gm45/northbridge.c | |
| parent | 66c22508c7ad0147a275b681db9133ff590a14b0 (diff) | |
nb/intel/gm45: Correctly cache TSEG
Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29866
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 0fd7fe5a92..a001a67914 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -221,22 +221,6 @@ static const char *northbridge_acpi_name(const struct device *dev) return NULL; } -u32 northbridge_get_tseg_base(void) -{ - return (u32)smm_region_start(); -} - -u32 northbridge_get_tseg_size(void) -{ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); - return decode_tseg_size(esmramc) << 10; -} - void northbridge_write_smram(u8 smram) { struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |