nb/intel/gm45: Fix panel-power-sequence clock divisor

We kept this value at it's default on the native graphics init path.
Maybe the Video BIOS path, too, I don't know if the VBIOS sets it.

The panel power sequencer uses the core display clock (CDCLK). It's
based on the HPLLVCO and a frequency selection we made during raminit.
The value written is the (actual divisor/2)-1 for a 100us timer.

v2: Fix unaligned mmio access inherited from Linux.

v3: Use MCHBAR8() instead. Also, the unaligned access might have
    worked after all.

Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17619
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 20 insertions, 2 deletions

diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 8938197815..3e9f508b70 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -611,6 +611,24 @@ static u8 vga_connected(u8 *mmio)
 	return 1;
 }
 
+static u32 get_cdclk(struct device *const dev)
+{
+	const u16 cdclk_sel =
+		pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK;
+	switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) {
+	case VCO_2666:
+	case VCO_4000:
+	case VCO_5333:
+		return cdclk_sel ? 333333333 : 222222222;
+	case VCO_3200:
+		return cdclk_sel ? 320000000 : 228571429;
+	default:
+		printk(BIOS_WARNING,
+		       "Unknown VCO frequency, using default cdclk.\n");
+		return 222222222;
+	}
+}
+
 static void gma_pm_init_post_vbios(struct device *const dev)
 {
 	const struct northbridge_intel_gm45_config *const conf = dev->chip_info;
@@ -635,8 +653,8 @@ static void gma_pm_init_post_vbios(struct device *const dev)
 
 	/* Setup Panel Power Cycle Delay */
 	if (conf->gpu_panel_power_cycle_delay) {
-		reg32 = gtt_read(PP_DIVISOR);
-		reg32 &= ~0x1f;
+		reg32 = (get_cdclk(dev) / 20000 - 1)
+			<< PP_REFERENCE_DIVIDER_SHIFT;
 		reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f;
 		gtt_write(PP_DIVISOR, reg32);
 	}