diff options
| author | Nico Huber <nico.h@gmx.de> | 2016-11-27 14:43:12 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2016-11-28 17:37:48 +0100 |
| commit | d85a71a75c35b5bf683939e320ff7a501f89f583 (patch) | |
| tree | 30f3e0306cb0de1367fe30ddd2d918df64bf4285 /src/northbridge/intel/gm45/gm45.h | |
| parent | 673a4d0f4d06bfb6556756c97300b4cea336d484 (diff) | |
nb/intel/gm45: Fix panel-power-sequence clock divisor
We kept this value at it's default on the native graphics init path.
Maybe the Video BIOS path, too, I don't know if the VBIOS sets it.
The panel power sequencer uses the core display clock (CDCLK). It's
based on the HPLLVCO and a frequency selection we made during raminit.
The value written is the (actual divisor/2)-1 for a 100us timer.
v2: Fix unaligned mmio access inherited from Linux.
v3: Use MCHBAR8() instead. Also, the unaligned access might have
worked after all.
Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17619
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/gm45/gm45.h')
| -rw-r--r-- | src/northbridge/intel/gm45/gm45.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index ae1863bdda..b9d2cb7299 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -260,6 +260,8 @@ enum { #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define HPLLVCO_MCHBAR 0x0c0f + #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ #define PMSTS_WARM_RESET (1 << 1) #define PMSTS_BOTH_SELFREFRESH (1 << 0) |