diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 00:36:31 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-07 20:20:00 +0000 |
| commit | f462b3d379198c968467053f570d6a40c9c8a715 (patch) | |
| tree | 06da018e6740df91f9d7fcbd9d18fa600efcc2dd /src/northbridge/intel/gm45/early_init.c | |
| parent | dd1fb4e38c209f4713d80ae192bd8f4cb4ed0e32 (diff) | |
nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors
These accessors can be reused for several other northbridges.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/early_init.c')
| -rw-r--r-- | src/northbridge/intel/gm45/early_init.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 86f71d6ff8..6e3ea2c7a3 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -10,13 +10,13 @@ void gm45_early_init(void) const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ - pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1); + pci_write_config32(d0f0, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); /* Setup DMIBAR. */ - pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1); + pci_write_config32(d0f0, D0F0_DMIBAR_LO, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); /* Setup EPBAR. */ - pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); + pci_write_config32(d0f0, D0F0_EPBAR_LO, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1); |