diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-06-09 18:13:34 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:48:44 +0200 |
| commit | 266a1f794dc28053e97794cbeb3f1a588137698b (patch) | |
| tree | 7cb11796fa351bd50d15af6be9508a15be223192 /src/northbridge/intel/gm45/chip.h | |
| parent | e7f35cd2924de7c9b2e8a74a50d35928b9da76a4 (diff) | |
nb/intel/raminit (native): Read PCI mmio size from devicetree
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/gm45/chip.h')
| -rw-r--r-- | src/northbridge/intel/gm45/chip.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index b537b93633..836d6bb737 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -26,6 +26,11 @@ struct northbridge_intel_gm45_config { u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ struct i915_gpu_controller_info gfx; + + /* + * Maximum PCI mmio size in MiB. + */ + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ |