CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM

The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.

TODO: Check TSEG alignment, it used for MTRR programming.

Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

4 files changed, 40 insertions, 18 deletions

diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
index 080a7f4946..ca6f345daf 100644
--- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc
+++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
@@ -20,11 +20,13 @@
 
 subdirs-y += fsp
 ramstage-y += northbridge.c
+ramstage-y += ram_calc.c
 ramstage-y += gma.c
 
 ramstage-y += acpi.c
 
 romstage-y += raminit.c
+romstage-y += ram_calc.c
 romstage-y += early_init.c
 romstage-y += report_platform.c
 romstage-y += ../../../arch/x86/lib/walkcbfs.S
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c
index adc69bcd89..fac635df10 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c
@@ -245,16 +245,6 @@ static void pci_domain_set_resources(device_t dev)
 	assign_resources(dev->link_list);
 }
 
-unsigned long get_top_of_ram(void)
-{
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-
-	/* Base of TSEG is top of usable DRAM */
-	u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0);
-	tom -= 0x200000;	/* 2MB for FSP HOB */
-	return (unsigned long) tom;
-}
-
 	/* TODO We could determine how many PCIe busses we need in
 	 * the bar. For now that number is hardcoded to a max of 64.
 	 * See e7525/northbridge.c for an example.
diff --git a/src/northbridge/intel/fsp_sandybridge/ram_calc.c b/src/northbridge/intel/fsp_sandybridge/ram_calc.c
new file mode 100644
index 0000000000..43a11051f4
--- /dev/null
+++ b/src/northbridge/intel/fsp_sandybridge/ram_calc.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <fsp_util.h>
+#include "northbridge.h"
+
+static uintptr_t smm_region_start(void)
+{
+	/* Base of TSEG is top of usable DRAM */
+	uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0);
+	return tom;
+}
+
+void *cbmem_top(void)
+{
+	return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
+}
diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c
index 19b48ca29b..868927430c 100644
--- a/src/northbridge/intel/fsp_sandybridge/raminit.c
+++ b/src/northbridge/intel/fsp_sandybridge/raminit.c
@@ -74,11 +74,3 @@ void report_memory_config(void)
 		       ((ch_conf >> 16) & 1) ? ", selected" : "");
 	}
 }
-
-unsigned long get_top_of_ram(void)
-{
-	/* Base of TSEG is top of usable DRAM */
-	u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0);
-	tom -= 0x200000;	/* 2MB for FSP HOB */
-	return (unsigned long) tom;
-}