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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-22 12:28:07 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-01-27 22:48:06 +0100
commitf1e3c763b3eef15dbfae73f485408a0dec230d00 (patch)
tree28682b0d4ad36063b3612c8a774af868a3e55878 /src/northbridge/intel/fsp_sandybridge/raminit.c
parent91fac61240612291f7be3362f7acad31803e8b03 (diff)
CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/fsp_sandybridge/raminit.c')
-rw-r--r--src/northbridge/intel/fsp_sandybridge/raminit.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c
index 19b48ca29b..868927430c 100644
--- a/src/northbridge/intel/fsp_sandybridge/raminit.c
+++ b/src/northbridge/intel/fsp_sandybridge/raminit.c
@@ -74,11 +74,3 @@ void report_memory_config(void)
((ch_conf >> 16) & 1) ? ", selected" : "");
}
}
-
-unsigned long get_top_of_ram(void)
-{
- /* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0);
- tom -= 0x200000; /* 2MB for FSP HOB */
- return (unsigned long) tom;
-}