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authorVladimir Serbinenko <phcoder@gmail.com>2015-05-29 16:33:49 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2015-06-10 05:33:18 +0200
commitf34082c0e3a6333e2a4cfc8c7715ecef552ac5a1 (patch)
tree4c8b63e2fc2eb604ead05d19c25e1a0a798b9834 /src/northbridge/intel/fsp_sandybridge/northbridge.h
parentf099e1bcff48d7d83c258c866c84a6eb90621434 (diff)
fsp_model_206ax: Use common i945-ivy tseg SMM init.
Change-Id: Iac390b565d709b11bc7a6631b11315994b6e2c3c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10466 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/fsp_sandybridge/northbridge.h')
-rw-r--r--src/northbridge/intel/fsp_sandybridge/northbridge.h11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index 6d4f83c5b6..4861254902 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -94,11 +94,6 @@
#define LAC 0x87 /* Legacy Access Control */
#define SMRAM 0x88 /* System Management RAM Control */
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRAME (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define TOM 0xa0
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
@@ -203,12 +198,6 @@
#ifndef __ASSEMBLER__
static inline void barrier(void) { asm("" ::: "memory"); }
-struct ied_header {
- char signature[10];
- u32 size;
- u8 reserved[34];
-} __attribute__ ((packed));
-
#define PCI_DEVICE_ID_SB 0x0104
#define PCI_DEVICE_ID_IB 0x0154