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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 19:20:16 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-06 09:41:43 +0100 |
| commit | 8e73821ce2603fd1b16cf32797904ddf2f2d9828 (patch) | |
| tree | a2b3ce6b86ac81b14c5e2c9575a81b8f9cc6c8d7 /src/northbridge/intel/fsp_sandybridge/early_init.c | |
| parent | 6220eec18816f816cae28c07c6afcaf1673d83c6 (diff) | |
intel/fsp_sandybridge: Switch to MMCONF_SUPPORT_DEFAULT
Untested.
Change-Id: I61ab1e5279c995f933971332673aa4ca0150e80c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17544
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/fsp_sandybridge/early_init.c')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/early_init.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/early_init.c b/src/northbridge/intel/fsp_sandybridge/early_init.c index 5ac1ac6304..5071def9a2 100644 --- a/src/northbridge/intel/fsp_sandybridge/early_init.c +++ b/src/northbridge/intel/fsp_sandybridge/early_init.c @@ -30,8 +30,6 @@ static void sandybridge_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); |