diff options
author | Martin Roth <gaumless@gmail.com> | 2014-04-25 15:09:27 -0600 |
---|---|---|
committer | Martin Roth <martin.roth@se-eng.com> | 2014-05-09 21:36:12 +0200 |
commit | 2dd3f877cc7926f5ac1cfd5a7e5d546c8be2121c (patch) | |
tree | 164e0f702179302236d8477d889804e405f143a2 /src/northbridge/intel/fsp_sandybridge/Makefile.inc | |
parent | a6427161c20bfb8319208dbbd08697a530a3839e (diff) |
cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
CPU - fsp_model_206ax:
- Remove Kconfig options and mark this as using the FSP.
- Use shared FSP cache_as_ram.inc file
Mainboard - intel/cougar_canyon2:
- Update to use the shared FSP header file.
- Modify to call copy_and_run() directly instead of returning to
cache_as_ram.inc.
Northbridge - fsp_sandybridge:
- remove mrccache, fsp_util.[ch]
- add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits.
- Update to use the shared FSP header file.
These changes were validated with FSP:
CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd
SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801
MD5: 24965382fbb832f7b184d3f24157abda
Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5636
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/northbridge/intel/fsp_sandybridge/Makefile.inc')
-rw-r--r-- | src/northbridge/intel/fsp_sandybridge/Makefile.inc | 27 |
1 files changed, 3 insertions, 24 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc index 5bc3d58afd..f5dbbe4e89 100644 --- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc +++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc @@ -2,7 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2010 Google Inc. -# Copyright (C) 2013 Sage Electronic Engineering, LLC. +# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -18,41 +18,20 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-y += fsp ramstage-y += northbridge.c ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c -ramstage-y += fsp_util.c -ramstage-$(CONFIG_ENABLE_FAST_BOOT) += mrccache.c romstage-y += raminit.c -romstage-y += fsp_util.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S -romstage-$(CONFIG_ENABLE_FAST_BOOT) += mrccache.c smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c -ifeq ($(CONFIG_HAVE_FSP_BIN),y) -# We don't ship an FSP, but booting without it is bound to fail -cbfs-files-y += fsp.bin -fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) -fsp.bin-position := $(CONFIG_FSP_LOC) -fsp.bin-type := 0xab -endif - -ifeq ($(CONFIG_ENABLE_FAST_BOOT),y) -$(obj)/mrc.cache: - dd if=/dev/zero count=1 \ - bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ - tr '\000' '\377' > $@ - -cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache -mrc.cache-position := 0xfff50000 -mrc.cache-type := 0xac -endif +INCLUDES += -I$(src)/northbridge/intel/fsp_sandybridge/fsp $(obj)/northbridge/intel/fsp_sandybridge/acpi.ramstage.o : $(obj)/build.h |