diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-21 16:20:55 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-01-06 13:09:54 +0000 |
| commit | e7377556cc33b10fdba6d956ac83d823478f5eb4 (patch) | |
| tree | 8843182316aed1730edb12aa0fbc18de4d3be414 /src/northbridge/intel/fsp_rangeley | |
| parent | c70eed1e6202c928803f3e7f79161cd247a62b23 (diff) | |
device: Use pcidev_path_on_root()
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index fcba7c1457..79775757b5 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -59,7 +59,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) DEVTREE_CONST config_t *config; printk(BIOS_DEBUG, "Configure Default UPD Data\n"); - dev = dev_find_slot(0, SOC_DEV_FUNC); + dev = pcidev_path_on_root(SOC_DEV_FUNC); config = dev->chip_info; /* Set SPD addresses */ |