diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-17 20:48:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 17:38:01 +0200 |
| commit | d4fea5c67587114f2be4c3235f4eb9c8d70df6ed (patch) | |
| tree | 988f7983b3a1c81fefe6054f4a00a3631fa6ba61 /src/northbridge/intel/fsp_rangeley/udelay.c | |
| parent | a3d15afc675b8030c692af6ff918d6b67255c2d7 (diff) | |
northbridge/intel/fsp_rangeley: Add space around operators
Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16631
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/fsp_rangeley/udelay.c')
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/udelay.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index e599e00482..5aca22974f 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -19,7 +19,7 @@ #include <cpu/x86/msr.h> /** - * Intel Rangeley CPUs always run the TSC at BCLK=100MHz + * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz */ /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. |