Revert "Remove FSP Rangeley SOC and mohonpeak board support"

This chip is still being used and should not have been deleted.  It's
a current intel chip, and doesn't even require an ME binary.

This reverts commit 959478a763c16688d43752adbae2c76e7764da45.

Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 48 insertions, 0 deletions

diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c
new file mode 100644
index 0000000000..181beb299f
--- /dev/null
+++ b/src/northbridge/intel/fsp_rangeley/raminit.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/io.h>
+#include <cbmem.h>
+#include <device/pci_def.h>
+#include "northbridge.h"
+#include <drivers/intel/fsp1_0/fsp_util.h>
+
+static uintptr_t smm_region_start(void)
+{
+	/*
+	 * Calculate the top of usable (low) DRAM.
+	 * The FSP's reserved memory sits just below the SMM region,
+	 * allowing calculation of the top of usable memory.
+	 */
+	uintptr_t tom = sideband_read(B_UNIT, BMBOUND);
+	uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
+	if (bsmmrrl) {
+		tom = bsmmrrl;
+	}
+
+	return tom;
+}
+
+void *cbmem_top(void)
+{
+	return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
+}