diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:37:28 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:45 +0000 |
| commit | c2c634a089fa990418c363e2ff2e5ff70bdd3580 (patch) | |
| tree | 042e376cee473f72f143ed76768f50536ab323ef /src/northbridge/intel/fsp_rangeley/port_access.c | |
| parent | 298619f6d9adde49b4279c906b0d20a41f919a61 (diff) | |
nb/sb/cpu: Drop Intel Rangeley support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I41589118579988617677cf48af5401bc35b23e05
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/northbridge/intel/fsp_rangeley/port_access.c')
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/port_access.c | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c deleted file mode 100644 index 75d1bb2b05..0000000000 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009-2010 iWave Systems - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <cpu/x86/lapic.h> -#include "northbridge.h" - -/* - * Restricted Access Regions: - * - * MCR - Message Control Register - * 31 24 16 8 4 0 - * ---------------------------------------------------------------------------- - * | | | Target | Write | | - * | Opcode | Port | register | byte | Reserved | - * | | | Address | Enables | | - * ---------------------------------------------------------------------------- - * - * MDR - Message Data Register - * 31 0 - * ---------------------------------------------------------------------------- - * | | - * | Data | - * | | - * ---------------------------------------------------------------------------- - */ - -#define MSG_OPCODE_READ (0x10 << 24) -#define MSG_OPCODE_WRITE (0x11 << 24) - -#define MCR 0xD0 -#define MDR 0xD4 -#define MCRE 0xD8 - -u32 sideband_read(int port, int reg) -{ - pci_write_config32(PCI_DEV(0, 0, 0), MCR, - (MSG_OPCODE_READ | (port << 16) | (reg << 8))); - return pci_read_config32(PCI_DEV(0, 0, 0), MDR); -} - -void sideband_write(int port, int reg, long data) -{ - pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); - pci_write_config32(PCI_DEV(0, 0, 0), MCR, - (MSG_OPCODE_WRITE | (port << 16) | (reg << 8) | (0xF << 4))); - pci_read_config32(PCI_DEV(0, 0, 0), MDR); -} |