diff options
| author | Martin Roth <gaumless@gmail.com> | 2014-05-21 14:20:38 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-07-30 19:00:15 +0200 |
| commit | 2963ae7fd49c7086ca9c4231f00a94e2f8a33080 (patch) | |
| tree | 8836147464d4ce337ba360391a99d49da5c66b8c /src/northbridge/intel/fsp_rangeley/chip.h | |
| parent | 09670265b63184f92d78fc8fe5311f3662cc528a (diff) | |
northbridge/intel: Add fsp_rangeley northbridge support
This adds the northbridge initialization pieces for Intel's Atom C2000
processor (Formerly Rangeley). It is intended to be used with the Intel
Atom C2000 FSP and does not contain all of the pieces that would
otherwise be required for initialization.
Not currently supported:
S3 suspend/resume
CAR memory Migration (No early cbmem console)
SMM
Change-Id: I7665212c892d9a08ecf35d7be70d0afe5fd2c77b
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/6369
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/intel/fsp_rangeley/chip.h')
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/chip.h | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h new file mode 100644 index 0000000000..24609a107e --- /dev/null +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _FSP_RANGELEY_CHIP_H_ +#define _FSP_RANGELEY_CHIP_H_ + +#include <arch/acpi.h> + +struct northbridge_intel_fsp_rangeley_config { + + /* Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1) */ + /* Valid values: 0 - 15 */ + uint8_t MrcRmtCpgcExpLoopCntValue; + /* Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1) */ + /* Valid values: 0 - 15 */ + uint8_t MrcRmtCpgcNumBursts; + /* DIMM SPD SMBus Addresses */ + uint8_t SpdBaseAddress_0_0; + uint8_t SpdBaseAddress_0_1; + uint8_t SpdBaseAddress_1_0; + uint8_t SpdBaseAddress_1_1; + +#define UPD_ENABLE 1 +#define UPD_DISABLE 0 + uint8_t EnableLan; + uint8_t EnableSata2; + uint8_t EnableSata3; + uint8_t EnableIQAT; + uint8_t EnableUsb20; + uint8_t PrintDebugMessages; + uint8_t Fastboot; + uint8_t EccSupport; + uint8_t SpdWriteProtect; + /* Enable = Memory Down, Disable = DIMM */ + uint8_t MemoryDown; + /* Enable the Rank Margin Tool, needs PrintDebugMessages */ + uint8_t MrcRmtSupport; + +#define BIFURCATION_4_4_4_4 0 +#define BIFURCATION_4_4_8 1 +#define BIFURCATION_8_4_4 2 +#define BIFURCATION_8_8 3 +#define BIFURCATION_16 4 + uint8_t Bifurcation; +}; + +#endif |