diff options
author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-17 02:46:24 +0100 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-18 02:11:06 +0100 |
commit | 5878bbd935c8cbd7c6d25ef72a5460f3262119e7 (patch) | |
tree | 5a8500e6c3d5afbbdf2e54e51f9ef46ad3a4d6d0 /src/northbridge/intel/e7520/e7520.h | |
parent | 61ed48c9233e0d74ef5c6847052662d075553691 (diff) |
Drop Intel E7520 and E7525 and related boards
There is no Cache As Ram for these boards, let's get rid of them.
Also drop unused dependencies
Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7836
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/intel/e7520/e7520.h')
-rw-r--r-- | src/northbridge/intel/e7520/e7520.h | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/src/northbridge/intel/e7520/e7520.h b/src/northbridge/intel/e7520/e7520.h deleted file mode 100644 index 61401e47ae..0000000000 --- a/src/northbridge/intel/e7520/e7520.h +++ /dev/null @@ -1,39 +0,0 @@ -#define IURBASE 0X14 -#define MCHCFG0 0X50 -#define MCHSCRB 0X52 -#define FDHC 0X58 -#define PAM 0X59 -#define DRB 0X60 -#define DRA 0X70 -#define DRT 0X78 -#define DRC 0X7C -#define DRM 0X80 -#define DRORC 0X82 -#define ECCDIAG 0X84 -#define SDRC 0X88 -#define CKDIS 0X8C -#define CKEDIS 0X8D -#define DDRCSR 0X9A -#define DEVPRES 0X9C -#define DEVPRES_D0F0 (1 << 0) -#define DEVPRES_D1F0 (1 << 1) -#define DEVPRES_D2F0 (1 << 2) -#define DEVPRES_D3F0 (1 << 3) -#define DEVPRES_D4F0 (1 << 4) -#define DEVPRES_D5F0 (1 << 5) -#define DEVPRES_D6F0 (1 << 6) -#define DEVPRES_D7F0 (1 << 7) -#define ESMRC 0X9D -#define SMRC 0X9E -#define EXSMRC 0X9F -#define DDR2ODTC 0XB0 -#define TOLM 0XC4 -#define REMAPBASE 0XC6 -#define REMAPLIMIT 0XC8 -#define REMAPOFFSET 0XCA -#define TOM 0XCC -#define EXPECBASE 0XCE -#define DEVPRES1 0XF4 -#define DEVPRES1_D0F1 (1 << 5) -#define DEVPRES1_D8F0 (1 << 1) -#define MSCFG 0XF6 |