diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-09 14:00:44 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-18 16:00:45 +0000 |
| commit | 799c3219146c8d246ef95f1fdb83dc7bc1f2be61 (patch) | |
| tree | e6dcc99fe3b577d28b602311232779eff8dda4cb /src/northbridge/intel/e7505 | |
| parent | 9cbbba68b650933cf552f9e1b969f08e463c641f (diff) | |
cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Diffstat (limited to 'src/northbridge/intel/e7505')
| -rw-r--r-- | src/northbridge/intel/e7505/memmap.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index b1ac3d1124..0d90175a5a 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -3,14 +3,16 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include <device/pci_ops.h> #include <arch/romstage.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <device/pci_ops.h> #include <program_loading.h> +#include <stdint.h> + #include "e7505.h" -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { const pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -19,7 +21,7 @@ void *cbmem_top_chipset(void) tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27; - return (void *)tolm; + return tolm; } void northbridge_write_smram(u8 smram); |