diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-09 09:37:49 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-15 05:31:29 +0000 |
| commit | 5bc641afebda5fd274ba713add4145651d9bc71d (patch) | |
| tree | 849f5712a83c5eb895ae3aee24a26509c8a8421b /src/northbridge/intel/e7505 | |
| parent | b3267e002e798e90ca09b11e42ea8949dccde2e7 (diff) | |
cpu/intel: Refactor platform_enter_postcar()
There are benefits in placing the postcar_frame structure
in .bss and returning control to romstage_main().
Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/e7505')
| -rw-r--r-- | src/northbridge/intel/e7505/memmap.c | 17 |
1 files changed, 3 insertions, 14 deletions
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index b954c6af74..c3b59e9415 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -43,17 +43,10 @@ void northbridge_write_smram(u8 smram) pci_write_config8(mch, SMRAMC, smram); } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - /* * Choose to NOT set ROM as WP cacheable here. * Timestamps indicate the CPU this northbridge code is @@ -62,14 +55,10 @@ void platform_enter_postcar(void) */ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ } |