diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-04-18 20:33:35 +0300 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-04-21 09:37:04 +0200 |
| commit | 97c064f0346874dcf02d4b2700a7e7c7913b24c9 (patch) | |
| tree | 4b54f54c2b3ba29bd55df69563fd990c442f105b /src/northbridge/intel/e7505/raminit.h | |
| parent | a8111cf980e01e9f8706024f06c05840b5fc8bcf (diff) | |
Intel e7505: enable ECC scrubbing
It takes about 3 seconds to scrub 8GiB DDR266 RAM.
After ECC scrub XIP cache is disabled for system stability. There is
very little to do in romstage after ECC scrub, especially when RAM
debug messages are turned off. So the delay caused by this is hardly
noticeable.
Cache for complete ROM is re-enabled before ramstage is decompressed,
and it has no unstability issues. So the code required to re-enable
cache for ROM currently already exists in cache-as-ram_ht.inc.
A Kconfig option HW_SCRUBBER enables the scrub to be run on hard
reboots and power-ons.
Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/905
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/northbridge/intel/e7505/raminit.h')
| -rw-r--r-- | src/northbridge/intel/e7505/raminit.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index df0e9291a3..a38d722d15 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -15,8 +15,8 @@ struct mem_controller { uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; -#ifndef __ROMCC__ -void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif +void e7505_mch_init(const struct mem_controller *memctrl); +void e7505_mch_scrub_ecc(unsigned long ret_addr); +void e7505_mch_done(const struct mem_controller *memctrl); #endif /* RAMINIT_H */ |