diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2011-10-21 12:57:59 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-10-28 22:01:03 +0200 |
| commit | b15975bf5a4a1b9ed4d83e2c8caf622d71a7e4d5 (patch) | |
| tree | 91e645b98fdfc145236b1d1f027b61e6895aff6b /src/northbridge/intel/e7505/raminit.h | |
| parent | 94a458626a9f12aa670926d633f445bebc1fb63c (diff) | |
copy e7501 component to e7505
Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/310
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/northbridge/intel/e7505/raminit.h')
| -rw-r--r-- | src/northbridge/intel/e7505/raminit.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h new file mode 100644 index 0000000000..df0e9291a3 --- /dev/null +++ b/src/northbridge/intel/e7505/raminit.h @@ -0,0 +1,22 @@ +#ifndef RAMINIT_H +#define RAMINIT_H + +#define MAX_DIMM_SOCKETS_PER_CHANNEL 4 +#define MAX_NUM_CHANNELS 2 +#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) + +struct mem_controller { + device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller + + // SMBus addresses of DIMM slots for each channel, + // in order from closest to MCH to furthest away + // 0 == not present + uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; + uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; +}; + +#ifndef __ROMCC__ +void sdram_initialize(int controllers, const struct mem_controller *ctrl); +#endif + +#endif /* RAMINIT_H */ |