diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-17 21:05:10 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 17:41:19 +0200 |
| commit | 9309552068c2cb4e0781b3268c740f93022b599e (patch) | |
| tree | 49ee6b2956041167e3c41784cd6cf2c72c312bc9 /src/northbridge/intel/e7505/raminit.c | |
| parent | cf13950736b65b944b4449e9ac4904665a0cc61a (diff) | |
northbridge/intel/e7505: Improve code formatting
Change-Id: I964512c0e913f7443f3dea859b01358645cfd8a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16632
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/e7505/raminit.c')
| -rw-r--r-- | src/northbridge/intel/e7505/raminit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 259fdd2a5f..8804ce8020 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1710,7 +1710,7 @@ static void sdram_enable(const struct mem_controller *ctrl) /* And for good luck 6 more CBRs */ RAM_DEBUG_MESSAGE("Ram Enable 8\n"); int i; - for (i=0; i<8; i++) + for (i = 0; i < 8; i++) do_ram_command(RAM_COMMAND_CBR, 0); /* 9 mode register set */ @@ -1823,7 +1823,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) /* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */ int i; pci_write_config8(MCHDEV, PAM_0, 0x30); - for (i=1; i<=6; i++) + for (i = 1; i <= 6; i++) pci_write_config8(MCHDEV, PAM_0 + i, 0x33); /* Conservatively say each row has 64MB of ram, we will fix this up later |