diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-17 14:16:03 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-02 21:55:31 +0000 |
| commit | 717b6e3151b6ea42aaa4b1ab2a708e143d098878 (patch) | |
| tree | f7caeb3a85a4cc965e62ca5ddf31217751976178 /src/northbridge/intel/e7505/Makefile.inc | |
| parent | 9e69c87317794219d7238eb87edc5e23e03803b4 (diff) | |
aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INIT
With implementation of LATE_CBMEM_INIT, top-of-low-memory
TOLM was adjusted late in ramstage. We do not allow that with
EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO
space is now used with statically set TOLM.
Also remove support code for the obsolete LATE_CBMEM_INIT
this northbridge used.
Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/e7505/Makefile.inc')
| -rw-r--r-- | src/northbridge/intel/e7505/Makefile.inc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc index 89a5b8cb70..57c870fde4 100644 --- a/src/northbridge/intel/e7505/Makefile.inc +++ b/src/northbridge/intel/e7505/Makefile.inc @@ -1,7 +1,9 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y) ramstage-y += northbridge.c +ramstage-y += memmap.c + romstage-y += raminit.c romstage-y += debug.c - +romstage-y += memmap.c endif |