- Update abuild.sh so it will rebuild successfull builds

- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
  enabled.  All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 31 insertions, 28 deletions

diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 43c354cfc1..ff65e29785 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -16,19 +16,14 @@ static void pci_domain_read_resources(device_t dev)
         unsigned reg;
 
         /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, 0);
-        resource->base  = 0x400;
+        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
         resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO;
-        compute_allocate_resource(&dev->link[0], resource,
-                IORESOURCE_IO, IORESOURCE_IO);
+        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
         /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, 1);
+        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
         resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM;
-        compute_allocate_resource(&dev->link[0], resource,
-                IORESOURCE_MEM, IORESOURCE_MEM);
+        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 }
 
 static void ram_resource(device_t dev, unsigned long index,
@@ -46,29 +41,37 @@ static void ram_resource(device_t dev, unsigned long index,
                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+	struct resource **best_p = gp;
+	struct resource *best;
+	best = *best_p;
+	if (!best || (best->base > new->base)) {
+		best = new;
+	}
+	*best_p = best;
+}
+
+static uint32_t find_pci_tolm(struct bus *bus)
+{
+	struct resource *min;
+	uint32_t tolm;
+	min = 0;
+	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+	tolm = 0xffffffffUL;
+	if (min && tolm > min->base) {
+		tolm = min->base;
+	}
+	return tolm;
+}
+
 static void pci_domain_set_resources(device_t dev)
 {
         struct resource *resource, *last;
 	device_t mc_dev;
         uint32_t pci_tolm;
 
-        pci_tolm = 0xffffffffUL;
-        last = &dev->resource[dev->resources];
-        for(resource = &dev->resource[0]; resource < last; resource++)
-        {
-                compute_allocate_resource(&dev->link[0], resource,
-                        BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
-
-                resource->flags |= IORESOURCE_STORED;
-                report_resource_stored(dev, resource, "");
-
-                if ((resource->flags & IORESOURCE_MEM) &&
-                        (pci_tolm > resource->base))
-                {
-                        pci_tolm = resource->base;
-                }
-        }
-
+        pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev->link[0].children;
 	if (mc_dev) {
 		/* Figure out which areas are/should be occupied by RAM.
@@ -175,16 +178,16 @@ static struct device_operations cpu_bus_ops = {
 
 static void enable_dev(struct device *dev)
 {
-        struct device_path path;
-
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
+		pci_set_method_conf1();
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;
         }
 }
 struct chip_operations northbridge_intel_e7501_ops = {
+	CHIP_NAME("Intel E7501 northbridge")
 	.enable_dev = enable_dev,
 };