- First stab at getting the ppc ports building and working.

- The sandpointx3+altimus has been consolidated into one directory for now.
- Added support for having different versions of the pci access functions
  on a per bus basis if needed.
  Hopefully I have not broken something inadvertently.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 1 insertions, 4 deletions

diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 6140c3f051..800831de3e 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -8,8 +8,6 @@
 #include <bitops.h>
 #include "chip.h"
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
 static void pci_domain_read_resources(device_t dev)
 {
         struct resource *resource;
@@ -67,7 +65,6 @@ static uint32_t find_pci_tolm(struct bus *bus)
 
 static void pci_domain_set_resources(device_t dev)
 {
-        struct resource *resource, *last;
 	device_t mc_dev;
         uint32_t pci_tolm;
 
@@ -157,6 +154,7 @@ static struct device_operations pci_domain_ops = {
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus      = &pci_cf8_conf1,
 };  
 
 static void cpu_bus_init(device_t dev)
@@ -181,7 +179,6 @@ static void enable_dev(struct device *dev)
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method_conf1();
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;