diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 00:36:31 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-07 20:20:00 +0000 |
| commit | f462b3d379198c968467053f570d6a40c9c8a715 (patch) | |
| tree | 06da018e6740df91f9d7fcbd9d18fa600efcc2dd /src/northbridge/intel/common/fixed_bars.h | |
| parent | dd1fb4e38c209f4713d80ae192bd8f4cb4ed0e32 (diff) | |
nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors
These accessors can be reused for several other northbridges.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/common/fixed_bars.h')
| -rw-r--r-- | src/northbridge/intel/common/fixed_bars.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/northbridge/intel/common/fixed_bars.h b/src/northbridge/intel/common/fixed_bars.h new file mode 100644 index 0000000000..d1b005bfae --- /dev/null +++ b/src/northbridge/intel/common/fixed_bars.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H +#define NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H + +_Static_assert(CONFIG_FIXED_MCHBAR_MMIO_BASE != 0, "MCHBAR base address is zero"); +_Static_assert(CONFIG_FIXED_DMIBAR_MMIO_BASE != 0, "DMIBAR base address is zero"); +_Static_assert(CONFIG_FIXED_EPBAR_MMIO_BASE != 0, "EPBAR base address is zero"); + +#include <stdint.h> + +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) + +#define DMIBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) + +#define EPBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) +#define EPBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) +#define EPBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) + +#endif /* ! NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H */ |